This invention relates to a silicon and silicon germanium based materials system and more specifically, to a novel epitaxial field effect transistor structure capable of high-speed low-noise, microwave, submillimeter-wave and millimeter-wave applications. Preferably, the epitaxial field effect transistor structure includes a high performance strained p-channel incorporating silicon, germanium, and silicon germanium layers to form a modulation-doped heterostructure.
In high speed and low noise device applications, the focus has been on designing and fabricating high electron mobility transistors (HEMTs) or modulation-doped field effect transistors (MODFETs) where carrier (eg. electrons, holes) conduction occurs in an undoped channel layer such that the carrier mobility is not limited by impurity scattering and high carrier mobility is achieved. In general, these high speed electronic devices are often used as low-noise amplifiers, power amplifiers, satellite receivers and transmitters operating in the microwave and rf regime, and the material of choice is usually the faster but more expensive III-V (e.g. GaAs) materials system and technology. A complicated and costly III-V materials technology is not very desirable in the semiconductor industry whereas a less-expensive SiGe materials system which is fully compatible with present Si technology is more desirable and far easier to integrate with existing Si-CMOS device technology.
One example of a material system compatible with Si technology is described in U.S. Pat. No. 5,019,882 which issued on May 28, 1991 to P. M. Solomon entitled xe2x80x9cGermanium Channel Silicon MOSFETxe2x80x9d and assigned to the assignee herein. In U.S. Pat. No. 5,019,882, a channel having improved carrier mobility comprises an alloy layer of silicon and germanium which is grown above a silicon substrate. The alloy layer is kept thin enough for proper pseudomorphic dislocation free growth. A layer of silicon is formed over the alloy layer and is oxidized partially through to form a dielectric layer. A gate region is formed over the silicon dioxide.
A second example of a high performance SiGe device structure compatible with Si technology, is described in U.S. Pat. No. 5,534,713 which issued on Jul. 9, 1996 to K. E. Ismail entitled xe2x80x9cComplementary Metal-Oxide Semiconductor Transistor Logic Using Strained Si/SiGe Heterostructure Layersxe2x80x9d and assigned to the assignee herein. In U.S. Pat. No. 5,534,713 a silicon CMOS transistor structure is described utilizing a buried SiGe channel under compressive strain with enhanced hole mobility for a p-channel device, and a buried Si channel under tensile strain with enhanced electron mobility for an n-channel device fabricated on a strained Si/SiGe heterostructure design. Further in U.S. Pat. No. 5,534,713 the proposed compressively-strained SiGe layer serving as a p-channel for the p-channel field effect transistor is described as having a composition germanium in the range from 50 to 100% and with a preferred composition of 80%. Thus far, prototype SiGe p-channel MODFETs utilizing this channel design and composition at the IBM Corporation have yielded hole mobilities only up to 1,000 cm2/Vs at room temperature. Consequently, in order to achieve an even higher hole mobility of greater than 1,000 cm2/Vs, a p-channel design with a composite or dual layer structure composed of a Ge layer (of 15-20 xc3x85 thick) together with a SiGe layer of 70-80% Ge (of 70-100 xc3x85 thick) is presented as the optimum p-channel structure to produce a higher hole mobility in a SiGe materials system.
In accordance with the present invention, a silicon and silicon germanium based epitaxial structure for a p-type field-effect transistor that utilizes a composite or a dual layer structure of substantially pure Ge and a SiGe layer in a p-channel region is described for forming a p-channel device comprising a semiconductor substrate, a first layer of relaxed Si1xe2x88x92xGex formed epitaxially on the substrate where the Ge fraction x is in the range from 0.35 to 0.5, a second layer of p doped Si1xe2x88x92xGee formed epitaxially on the first layer, a third layer of undoped Si formed epitaxially on the second layer whereby the Si layer is under tensile strain and remains commensurate with respect to the top of the first relaxed Si1xe2x88x92xGex layer, a fourth layer of undoped Si1xe2x88x92xGex formed epitaxially on the third layer, a fifth layer of undoped Ge formed epitaxially on the fourth layer whereby the Ge layer is under compressive strain and remains commensurate with respect to the top of the first relaxed Si1xe2x88x92wGew layer, a sixth layer of undoped Si1xe2x88x92yGey formed epitaxially on the fifth layer where the Ge fraction w is in the range from 0.5 to less than 1.00 and where wxe2x88x92x greater than 0.2 whereby the Si1xe2x88x92wGew layer is under compressive strain, and a seventh layer of undoped Si1xe2x88x92xGex formed epitaxially on the fifth layer. A metal layer alone to form a Schottky barrier or a dielectric and metal layer may be formed and patterned over the seventh layer to form the gate of the p-channel field effect transistor while the drain and source regions may be formed by forming p regions on either side of the gate in the layered structure. This layered structure design forms a modulation-doped heterostructure whereby the supply layer or the second p-doped Si1xe2x88x92xGex layer is located below the active composite channel of layers of five and six. Furthermore, in this layered device structure, the spacer layer which separate the active channel from the supply layer employs a dual layer comprising the third layer of undoped Si and the fourth layer of undoped Si1xe2x88x92xGex.
The invention further provides a method for forming and a p-channel field effect transistor having increased hole mobility in its channel comprising a semiconductor substrate, a first layer of relaxed Si1xe2x88x92xGex formed epitaxially on the substrate where x is in the range from 0.35 to 0.5, a second layer of p doped Si1xe2x88x92xGex formed epitaxially on the first layer, a third layer of undoped Si1xe2x88x92xGex formed epitaxially on the second layer, a fourth layer of undoped Ge formed epitaxially on the third layer whereby the Ge layer is commensurate with respect to the top of the first relaxed Si1xe2x88x92wGew layer, a fifth layer of undoped Si1xe2x88x92yGey formed epitaxially on the fourth layer where the Ge fraction w is in the range from 0.5 to less than 1.00 and the fifth Si1xe2x88x92wGew layer is under compressive strain, and a sixth layer of undoped Si1xe2x88x92xGex formed epitaxially on the fifth layer. This layered structure design describes a modulation-doped heterostructure whereby the supply layer p-doped Si1xe2x88x92xGex second layer is separated from the active composite channel in the fourth and fifth layers by a single spacer third layer design of Si or Si1xe2x88x92xGex.
The invention further provides a method and a p-channel field effect transistor having increased hole mobility in its channel comprising a semiconductor substrate, a first layer of relaxed Si1xe2x88x92xGex formed epitaxially on the substrate where x is in the range from 0.35 to 0.5, a second layer of undoped Ge formed epitaxially on the top of the first layer whereby the Ge layer is commensurate with respect to the top of the first relaxed Si1xe2x88x92xGex layer, a third layer of undoped Si1xe2x88x92wGew formed epitaxially on the second layer where the Ge fraction w is in the range from 0.5 to less than 1.00 and the third Si1xe2x88x92wGew layer is under compressive strain, a fourth layer of undoped Si1xe2x88x92xGex formed epitaxially on the third layer, and a fifth layer of p-doped Si1xe2x88x92xGex formed epitaxially on the fourth layer. This layered structure design describes a modulation-doped heterostructure whereby the supply layer or the fifth layer of p-doped Si1xe2x88x92xGex is located above the active composite channel comprising the second and third layer. Likewise, the supply layer or the fifth layer of p-doped Si1xe2x88x92xGex can be further separated above the active composite channel of the second and third layer with the addition of a Si spacer layer between the third and fourth layer, or alternatively between the fourth and fifth layer.
The invention further provides a method and a structure for a relaxed (greater than 90%) Si1xe2x88x92xGex buffer layer comprising a semiconductor substrate, a first layer of partially relaxed (less than 50%) Si1xe2x88x92xGex formed epitaxially by stepwise grading (or linear grading) where the Ge content of the layers is increased in a stepwise fashion (or in a linear fashion) starting on a and x is in the range of 0.1 to 0.9, a second layer of Si1xe2x88x92yGey formed epitaxially on the first layer where y=x+z and z is in the range from 0.01 to 0.1 which serves to xe2x80x9cover relaxxe2x80x9d the second layer to an equivalent composition and having a lattice spacing corresponding to a composition greater than x, and a third layer of Si1xe2x88x92xGex formed epitaxially on the second layer whereby Si1xe2x88x92xGex layer is now more relaxed as compared to the original, partially relaxed Si1xe2x88x92xGex first layer. The extent of additional relaxation due to this xe2x80x9cover shootxe2x80x9d second layer of Si1xe2x88x92yGey does depend on the thickness of this second layer which in turn is limited by its critical thickness on the initial partially relaxed Si1xe2x88x92xGex first layer.
The invention further provides a p-type field-effect transistor can be fabricated on one of the previously described layer structures where the conducting channel of the device is composed of a composite or dual layer structure comprising a substantially pure Ge layer and a SiGe layer. The field-effect transistor is isolated by regions created by selectively removing the top barrier layer, the conducting dual layer channel, the undoped spacer regions and the p-type doping region such that a two-dimensional channel is formed only within an isolated active device region. A gate electrode consisting of a conducting stripe may be formed directly on the wafer surface above the active device region, and source and drain electrodes may be formed by making Ohmic contact to the conducting dual layer channel on either side of the gate electrode within the active device region.
It is an object of this invention to provide a p-type modulation-doped field-effect transistor (MODFET) that is fabricated on a composite or dual-layer structure comprising substantially pure Ge layer and a SiGe layer.
It is an object of the invention to provide a layered structure which allows for p-channel field effect transistors to be formed having a channel with a unique composition profile as a function of depth.
It is a further object of the invention to provide a p-channel device where the active channel is a composite or dual layer structure composed of a thin Ge layer together with a SiGe layer.
It is a further object of the invention to provide p-channel devices where the composite channel structure takes advantage of the higher compressive strain with the benefits of higher carrier mobility and a higher barrier or a deeper confining channel for hole carriers as compared to a channel with a single SiGe layer.
It is a further object of the invention to provide a buried composite channel of a Ge layer with a SiGe layer under compressive strain for higher carrier mobility in a p-channel device.
It is a further object of the invention to provide a p-channel device where the spacer layer is a composite or dual layer design composed of a thin Si layer together with a SiGe layer.
It is further object of the invention to provide a layered structure and process for making where a desired relaxed SiGe layer can be more fully relaxed by the addition of one or more over shoot layers in the grade-up composition of the SiGe buffer structure.
It is a further object of the invention to provide a p-MODFET with higher hole mobility compared to the prior art, such as bulk Si p-MOSFETs and single-channel SiGe p-MODFETs.
It is a further object of the invention to provide a p-MODFET with enhanced high-frequency operation compared to bulk Si p-MOSFETs or compared to single-channel SiGe p-MODFETs due to higher carrier mobility.